Semiconductor package

A semiconductor package comprising:

• a package substrate;
• an interposer on the package substrate and comprising first upper pads, the first upper pads comprising a first set of upper pads and a second set of upper pads;
• a first semiconductor chip on the interposer and comprising first lower pads respectively connected to the first set of upper pads;
• a second semiconductor chip on the interposer and spaced apart from the first semiconductor chip, the second semiconductor chip comprising second lower pads respectively connected to the second set of upper pads;
• a plurality of first protruding structures in a first region of a first top surface of the first semiconductor chip, the plurality of first protruding structures being spaced apart by a first distance;
• and
• a plurality of second protruding structures spaced apart by a second distance that is less than the first distance, the plurality of second protruding structures being spaced apart from the plurality of first protruding structures,
• wherein the first top surface of the first semiconductor chip comprises a second region that does not overlap the first region,
• wherein a second top surface of the second semiconductor chip comprises a third region, and
• wherein the plurality of second protruding structures are in at least one of the second region and the third region.

A semiconductor package comprising:

• a package substrate comprising upper substrate pads exposed at a top surface of the package substrate;
• an interposer on the package substrate and comprising first upper pads, the first upper pads comprising a first set of upper pads and a second set of upper pads;
• a first semiconductor chip on the interposer, the first semiconductor chip comprising:
• first lower bumps;
• and
• first lower pads respectively connected to the first set of upper pads;
• a second semiconductor chip on the interposer and spaced apart from the first semiconductor chip, the second semiconductor chip comprising:
• second lower bumps;
• and
• second lower pads respectively connected to the second set of upper pads;
• a plurality of first pins in a first region of a first top surface of the first semiconductor chip, the plurality of first pins being spaced apart by a first distance;
• and
• a plurality of second pins spaced apart by a second distance that is less than the first distance,
• wherein the interposer further comprises:
• third lower bumps;
• and
• third lower pads respectively connected to the upper substrate pads,
• wherein the first lower bumps are between the first set of upper pads and the first lower pads,
• wherein the second lower bumps are between the second set of upper pads and the second lower pads,
• wherein the plurality of first pins and the plurality of second pins comprise a metal material,
• wherein the first top surface of the first semiconductor chip comprises a second region that does not overlap the first region,
• wherein a second top surface of the second semiconductor chip comprises a third region,
• wherein the plurality of second pins are in at least one of the second region and the third region,
• wherein the first semiconductor chip comprises a logic semiconductor chip, and
• wherein the second semiconductor chip comprises at least one memory semiconductor chip.