Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a dielectric substrate;
• an etch stop layer on the dielectric substrate;
• a channel pattern on the etch stop layer, wherein the channel pattern comprises a plurality of semiconductor patterns that are stacked and spaced apart from each other,
• a source/drain pattern coupled to the channel pattern;
• a gate electrode on the channel pattern, wherein the gate electrode comprises a plurality of inner electrodes that are correspondingly interposed between the plurality of semiconductor patterns;
• a lower power line below the dielectric substrate;
• and
• a backside contact that penetrates the dielectric substrate and electrically couples the lower power line to the source/drain pattern,
• wherein the etch stop layer comprises silicon doped with at least one of oxygen (O) and carbon (C), and
• wherein the etch stop layer is between the dielectric substrate and a lowermost electrode of the plurality of inner electrodes.

A semiconductor device, comprising:

• a dielectric substrate;
• an etch stop layer on the dielectric substrate;
• a channel pattern on the etch stop layer, wherein the channel pattern comprises a plurality of semiconductor patterns that are stacked and spaced apart from each other,
• a source/drain pattern coupled to the channel pattern;
• a gate electrode on the channel pattern;
• a gate dielectric layer between the gate electrode and the channel pattern;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer dielectric layer that covers the source/drain pattern and the gate capping pattern;
• a gate contact that penetrates the interlayer dielectric layer and the gate capping pattern and is electrically coupled to the gate electrode;
• a first metal layer on the interlayer dielectric layer, wherein the first metal layer comprises a first wiring line electrically coupled to the gate contact;
• a lower power line below the dielectric substrate;
• and
• a backside contact that penetrates the dielectric substrate and electrically couples the lower power line to the source/drain pattern,
• wherein the backside contact comprises:
• an epitaxial pattern coupled to a lower portion of the source/drain pattern;
• a contact plug coupled to the lower power line;
• and
• a metal-semiconductor compound layer between the epitaxial pattern and the contact plug, and
• wherein a concentration of impurities in the epitaxial pattern is greater than a maximum concentration of impurities in the source/drain pattern.