Method and apparatus for manufacturing semiconductor chip with chip outline of various shapes at wafer level
AssigneeSeoul National University R&Db Foundation
InventorsTaehyun Kim, Kwangyeul Choi
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Abstract
A method of manufacturing a semiconductor chip at a wafer level is disclosed. The method includes performing a plasma dicing process based on a predetermined shape of an outline of each of a plurality of semiconductor chips such that a dicing line along a portion of the outline extends throughout a wafer, and performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip including a connection area between adjacent ones of the semiconductor chips is cut along a straight line.
Claims15
A method of manufacturing a semiconductor chip at a wafer level, comprising:
- performing a plasma dicing process based on a predetermined shape of an outline of each of a plurality of semiconductor chips such that a dicing line along a portion of the outline extends throughout a wafer;
- and
- performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line.
An apparatus for manufacturing a semiconductor chip at a wafer level, comprising:
- a controller configured to determine a shape of an outline of a semiconductor chip;
- a plasma dicing module configured to perform a plasma dicing process in which a dicing line along a portion of an outline of each of a plurality of semiconductor chips extends throughout a wafer, based on the outline shape of the semiconductor chip;
- and
- a blade dicing module configured to perform a blade dicing process in which a remaining portion of the outline of each of the plurality of semiconductor chips comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line.
Dependencies are inferred from the claim text.