Memory device

A memory device comprising:

• a memory cell configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or greater);
• a select transistor connected to the memory cell;
• a bit line connected to the select transistor;
• and
• a sequencer configured to execute a write operation having a first program operation and a loop process, the loop process including a second program operation and a verify operation, wherein
• the sequencer is further configured to
• in the first program operation in which the memory cell is a program target, apply a first voltage to the select transistor while applying a first program voltage to the memory cell,
• in the second program operation in which the memory cell is a program target, apply a second voltage lower than the first voltage to the select transistor while applying a second program voltage to the memory cell, and
• in the write operation, execute the first program operation with the memory cell set to be written or be write-inhibited according to data to be written in the memory cell, and store the data in the memory cell by the loop process.