Selective and Dynamic Deployment of Error Correction Code Techniques in Integrated Circuit Memory Devices

A method, comprising:

• configuring a plurality of memory cells in a memory device as a plurality of groups, wherein each of the groups is configured to provide a plurality of planes of bit storage, and wherein each of the planes is configured to store at least a codeword of an error correction code technique, the codeword having a predetermined size;
• determining that a bit error rate of the plurality of memory cells is above a threshold;
• reconfiguring, in response to the bit error rate being above the threshold, the plurality of memory cells to store codewords in first planes provided by the plurality of memory cells and store redundant data, generated from the codewords stored in the first planes, in at least one second plane provided by the plurality of memory cells.

A non-transitory computer storage medium storing instructions which, when executed on a computing device, cause the computing device to perform a method, comprising:

• configuring a plurality of memory cells in a memory device as a plurality of groups, wherein each of the groups is configured to provide a plurality of planes of bit storage, and wherein each of the planes is configured to store at least a codeword of an error correction code technique, the codeword having a predetermined size;
• determining that a bit error rate of the plurality of memory cells is above a threshold;
• reconfiguring, in response to the bit error rate being above the threshold, the plurality of memory cells to store codewords in first planes provided by the plurality of memory cells and store redundant data, generated from the codewords stored in the first planes, in at least one second plane provided by the plurality of memory cells.