# US 2024/0265960 A1 · Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays

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- Number: US 2024/0265960 A1
- Document ID: US20240265960A1
- Status: Published application
- Kind: A1
- Application number: 18/606,333
- Filed: 2024-03-15
- Published: 2024-08-08
- Earliest claimed: 2016-04-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Durai Vishak Nirmal Ramaswamy; Wayne Kinney
- Web page: https://patentgrep.com/patent/US20240265960A1

## CPC

- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2273: {Reading or sensing circuits or methods}
- H10B 51/30: characterised by the memory core region
- H10B 53/30: characterised by the memory core region
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- G11C 11/2257: {Word-line or row circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

## Claims

### Claim at position 1

1: A method of forming a ferroelectric transistor, comprising:
forming gate dielectric material configured as a first container, the first container having a first opening extending into the dielectric material and being defined by a first inner bottom surface and a first inner sidewall surface extending orthogonally relative to the first inner bottom surface;
forming a metal-containing material configured as a second container nested within said first opening, the second container having a second opening extending into the metal containing material and being defined by a second inner bottom surface with an area less than the first inner surface and having a second inner sidewall surface extending orthogonally relative to the second inner;
forming a ferroelectric material configured as a third container nested within the second opening, the third container having a third inner bottom surface with an area less than the second inner surface and having a third inner sidewall surface extending orthogonally relative to the third inner bottom surface;
forming a gate material within the third container, wherein a common sidewall surface extends orthogonally relative to the first, second and third inner bottom surfaces; and
forming an insulative sidewall spacer material along the common sidewall surface in direct physical contact with each of the metal-containing material, the gate dielectric material, the ferroelectric material and the gate material.

### Claim at position 2 (depends on 1)

2: The method of claim 1 wherein the first, second and third containers are elbow-shaped.

### Claim at position 3 (depends on 1)

3: The method of claim 1 wherein an edge of the second container is inset relative to an edge of the first container.

### Claim at position 4 (depends on 3)

4: The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by about a same amount as the edge of the second container is inset relative to the edge of the first container.

### Claim at position 5 (depends on 3)

5: The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by a greater amount than the edge of the second container is inset relative to the edge of the first container.

### Claim at position 6 (depends on 3)

6: The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by about a lesser amount than the edge of the second container is inset relative to the edge of the first container.