Amplifier Circuit and Display Apparatus Having the Same

A display apparatus comprising:

• a display panel including a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels;
• a gate driver configured to drive the plurality of gate lines of the display panel;
• and
• a data driver configured to drive the plurality of data lines of the display panel, the data driver including an amplifier circuit that amplifies a data voltage, the amplifier circuit including:
• a first stage including a first input terminal and a second input terminal, the first input terminal connected to an output terminal of the amplifier circuit that outputs the data voltage;
• a second stage connected to the first stage and configured to amplify the data voltage, the second stage including a pull-up node and a pull-down node;
• a third stage including the output terminal of the amplifier circuit that is connected to the first input terminal of the first stage, a pull-up PMOS transistor having a gate electrode connected to the pull-up node of the second stage, a pull-down NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified data voltage supplied from the second stage while the pull-up PMOS transistor is turned on or a pull-down driving of the amplified data voltage supplied from the second stage while the pull-down NMOS transistor is turned on;
• a first boosting circuit including a first boosting PMOS transistor having a gate electrode connected to the pull-up node included in the second stage and the gate electrode of the pull-up PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the first boosting PMOS transistor is turned on;
• and
• a second boosting circuit including a first boosting NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the pull-down NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the first boosting NMOS transistor is turned on.