Semiconductor device and a method of manufacturing the same

A semiconductor device comprising:

• a plurality of power interconnection lines on a substrate, the power interconnection lines arranged in a first direction, and the power interconnection lines extending in a second direction in parallel to each other;
• a plurality of logic cells two-dimensionally arranged on the substrate;
• a plurality of tab cells arranged in the first direction on the substrate;
• and
• a power delivery network layer under the substrate,
• wherein the plurality of tab cells comprises,
• a plurality of through-vias electrically connected to the plurality of power interconnection lines, respectively, and
• a plurality of lower through-vias electrically connecting the plurality of through-vias to the power delivery network layer, respectively,
• wherein the power delivery network layer is configured to apply voltages to the plurality of power interconnection lines through the through-vias and the lower through-vias,
• wherein each of the through-vias comprises,
• a first metal pattern being in contact with a corresponding one of the lower through-vias;
• and
• a second metal pattern stacked on the first metal pattern, and
• wherein a resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.

A semiconductor device comprising:

• a first power interconnection line and a second power interconnection line on a substrate, the first and second power interconnection lines spaced apart from each other in a first direction, and the first and second power interconnection lines extending in a second direction in parallel to each other;
• a logic cell and a tab cell between the first and second power interconnection lines, the logic cell and the tab cell adjacent to each other in the second direction;
• a first active pattern and a second active pattern on the logic cell, the first and second active patterns spaced apart from each other in the first direction;
• a first channel pattern and a first source/drain pattern on the first active pattern;
• a second channel pattern and a second source/drain pattern on the second active pattern, the second source/drain pattern having a conductivity type different from that of the first source/drain pattern;
• a gate electrode on the first and second channel patterns;
• a gate insulating layer between the gate electrode and the first and second channel patterns;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer covering the first and second source/drain patterns and the gate capping pattern;
• an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first and second source/drain patterns;
• a metal-semiconductor compound layer between the active contact and the at least one of the first and second source/drain patterns;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
• a first through-via and a second through-via on the tab cell, the first and second through-vias electrically connected to the first and second power interconnection lines, respectively;
• a power delivery network layer on a bottom surface of the substrate;
• and
• a first lower through-via and a second lower through-via between the power delivery network layer and the first and second through-vias, respectively,
• wherein each of the first and second through-vias comprises,
• a first metal pattern being in contact with a corresponding one of the first and second lower through-vias, and
• a second metal pattern stacked on the first metal pattern, and
• wherein the first metal pattern and the second metal pattern include different metals.