Complementary Field Effect Transistors and Methods of Forming the Same

A device comprising:

• a lower transistor comprising:
• a lower semiconductor nanostructure;
• a lower source/drain region adjacent the lower semiconductor nanostructure;
• and
• a lower source/drain contact adjacent the lower source/drain region;
• an upper transistor above the lower transistor, the upper transistor comprising:
• a upper semiconductor nanostructure;
• a upper source/drain region adjacent the upper semiconductor nanostructure;
• and
• a upper source/drain contact adjacent the upper source/drain region;
• and
• an isolation dielectric between the lower source/drain contact and the upper source/drain contact.

A method comprising:

• forming a recess in a first semiconductor nanostructure;
• forming a stop material in the recess;
• growing a first epitaxial source/drain region on the stop material and in the recess, the first epitaxial source/drain region disposed on a sidewall of the first semiconductor nanostructure;
• forming a first source/drain contact on the stop material and in the recess, the first source/drain contact disposed on a sidewall of the first epitaxial source/drain region;
• and
• forming an isolation dielectric on the first source/drain contact.