Laterally-gated transistors and lateral schottky diodes with integrated lateral field plate structures

A field-effect transistor (FET), comprising:

• a substrate;
• a source electrode and a drain electrode disposed on the substrate;
• a channel layer;
• a gate electrode structure comprising:
• a gate electrode in contact with the channel layer;
• a first lateral field plate adjacent to one side of the gate electrode;
• and
• a second lateral field plate adjacent to an opposite side of the gate electrode;
• a third lateral field plate disposed adjacent to the first lateral field plate;
• and
• a fourth lateral field plate disposed adjacent to the second lateral field plate;
• wherein the first and second lateral field plates are disposed in a symmetrical arrangement relative to the gate electrode;
• and
• a first dielectric layer disposed between the first and second lateral field plates and the channel layer;
• and
• wherein the first and second lateral field plates are in contact with the first dielectric layer and are configured to modulate an electric field proximal to the gate electrode proximal to at least one of the drain electrode or the source electrode, or both the drain electrode and the source electrode.

A field-effect transistor (FET), comprising:

• a substrate;
• a source electrode and a drain electrode disposed on the substrate;
• a channel layer;
• an aperture defined in the substrate to a depth extending to the channel layer, wherein the apertures define sidewalls;
• a gate electrode structure comprising:
• a gate electrode in contact with the channel layer;
• a first lateral field plate adjacent to one side of the gate electrode;
• and
• a second lateral field plate adjacent to an opposite side of the gate electrode;
• wherein the first and second lateral field plates are disposed in a symmetrical arrangement relative to the gate electrode;
• and
• a first dielectric layer disposed on the sidewalls except in lateral gaps disposed in the first dielectric layer configured to receive a bottom portion of the gate electrode such that the gate electrode is in lateral contact with the channel layer;
• and
• wherein the first and second lateral field plates are in contact with the first dielectric layer and are configured to modulate an electric field proximal to the gate electrode proximal to at least one of the drain electrode or the source electrode, or both the drain electrode and the source electrode.