Super junction semiconductor power device

A super junction semiconductor power device, comprising:

• an n-type drain region, an n-type drift region, and a plurality of p-type columns, wherein a width of each of the plurality of p-type columns is equal, and spacing between two adjacent p-type columns of the plurality of p-type columns is equal;
• and
• tops of the plurality of p-type columns are provided with a plurality of p-type body regions respectively, and the plurality of p-type body regions are in one-to-one correspondence with the plurality of p-type columns;
• widths of the plurality of p-type body regions are equal;
• and an n-type source region is provided in each of the plurality of p-type body regions;
• a gate structure configured to control a current channel between the n-type source region and the n-type drift region to turn on and turn off;
• and
• a plurality of junction field-effect transistor regions located on the n-type drift region and between adjacent p-type body regions of the plurality of p-type body regions, wherein the plurality of JFET regions are provided with at least two different widths.