Low resistance fill metal layer material as stressor in metal gates

A method, comprising:

• forming a first plurality of suspended semiconductor layers in a first region of a semiconductor substrate, and a second plurality of suspended semiconductor layers in a second region of the semiconductor substrate, wherein each of the first and the second plurality of suspended semiconductor layers is spaced away from one another;
• forming a gate dielectric layer to circumferentially wrap the first plurality of suspended semiconductor layers and the second plurality of suspended semiconductor layers;
• forming a work function metal layer over a portion of the gate dielectric layer to circumferentially wrap the second plurality of suspended semiconductor layers;
• and
• forming a fill metal layer on and directly contacting the gate dielectric layer in the first region and the work function metal layer in the second region,
• wherein the forming of the fill metal layer includes performing a deposition process at an elevated temperature is sufficient to generate a tensile stress asserted by the fill metal layer on the first plurality of suspended semiconductor layers when cooled down,
• wherein the fill metal layer includes aluminum (Al).

An integrated circuit (IC) device, comprising:

• a semiconductor substrate having a first transistor region and a second transistor region, the first transistor region includes first source/drain features doped with a first dopant, the second transistor region includes second source/drain features doped with a second dopant, the first and second dopants are opposite type dopants;
• a first plurality of stacked semiconductor layers in the first transistor region and a second plurality of stacked semiconductor layers in the second transistor region;
• a gate dielectric layer that wraps around each of the first and second plurality of stacked semiconductor layers;
• a first metal gate in the first transistor region, the first metal gate having a work function metal layer and a first fill metal layer, wherein the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer wraps around and is in direct contact with the work function metal layer;
• a second metal gate in the second transistor region, the second metal gate having a second fill metal layer that wraps around and is in direct contact with the gate dielectric layer;
• a first gate contact feature over and directly contacting the first fill metal layer of the first metal gate;
• and
• a second gate contact feature over and directly contacting the second fill metal layer of the second metal gate.