US 2024/0258302 A1 · SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION

Abstract

Some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. The semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. The discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. During a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.

Claims19

Dependent claims

A semiconductor die package, comprising:

a first integrated circuit die, comprising:
a trench capacitor;
a first seal ring segment;
and
a second seal ring segment that is electrically isolated from the first seal ring segment;
a second integrated circuit die connected with the first integrated circuit die and comprising:
a power management integrated circuit, comprising:
a first voltage terminal corresponding to a first polarity;
and
a second voltage terminal corresponding to a second polarity that is opposite the first polarity;
a first electrically conductive trace connecting the trench capacitor, the first seal ring segment, and the first voltage terminal;
and
a second electrically conductive trace connecting the trench capacitor, the second seal ring segment, and the second voltage terminal.

10 more elements

Dependencies are inferred from the claim text.

Semiconductor die package and methods of formation

Life of this patent

Semiconductor die package and methods of formation

Life of this patent

Abstract

Claims19