Forming esd devices using multi-gate compatible processes

A semiconductor device, comprising:

• a stack of first semiconductor layers and second semiconductor layers alternatingly disposed in a vertical direction, the first semiconductor layers having a first material composition and the second semiconductor layers having a second material composition different from the first material composition;
• a first doped region in the stack, the first doped region having a first dopant of a first conductivity type;
• a second doped region in the stack, the second doped region having a second dopant of a second conductivity type opposite the first conductivity type;
• a first contact disposed on and in electrical coupling with the first doped region;
• a second contact disposed on and in electrical coupling with the second doped region;
• a frontside multilayer interconnect structure disposed above the stack;
• and
• a backside multilayer interconnect structure disposed under the stack, wherein the first contact is in electrical coupling with the frontside multilayer interconnect structure.

A method of manufacturing a semiconductor device, comprising:

• providing a structure having a substrate and a stack protruding from the substrate, the stack having first semiconductor layers and second semiconductor layers alternatingly arranged in a vertical direction, the first and second semiconductor layers having different material compositions;
• depositing an isolation feature on sidewalls of the stack;
• implanting a first dopant into a first region of the stack, the first dopant having a first conductivity type;
• implanting a second dopant into a second region of the stack, the second dopant having a second conductivity type opposite the first conductivity type;
• and
• forming a first metal gate structure above the first region;
• forming a second metal gate structure above the second region, wherein at least a portion of the first region and a portion of the second region are between the first and second metal gate structures;
• depositing a dielectric layer between the first and second metal gate structures;
• forming a first contact through the dielectric layer and landing on the first region;
• and
• forming a second contact through the dielectric layer and landing on the second region.