Integrated circuit package and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
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Abstract
In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
Claims20
A device comprising:
- a processor device;
- a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds, the first memory device comprising a first conductive via;
- a first dielectric layer laterally surrounding the first memory device, a sidewall of the first dielectric layer being laterally coterminous with a sidewall of the processor device;
- and
- a second conductive via extending through the first dielectric layer, the second conductive via connected to the processor device, a top surface of the second conductive via being planar with a top surface of the first dielectric layer and a top surface of the first conductive via.
A device comprising:
- a processor device having a front side;
- a first memory device having a front side and a back side opposite the front side, the front side of the first memory device bonded to the front side of the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds;
- a first dielectric layer laterally surrounding the first memory device;
- first conductive vias extending through the first dielectric layer, the first conductive vias connected to the front side of the processor device;
- a second memory device having a front side and a back side opposite the front side, the front side of the second memory device bonded to the first conductive vias and the back side of the first memory device by metal-to-metal bonds, the front side of the second memory device bonded to the first dielectric layer and the back side of the first memory device by dielectric-to-dielectric bonds, the first memory device being a different type of memory device than the second memory device;
- and
- a second dielectric layer laterally surrounding the second memory device, a sidewall of the second dielectric layer being laterally coterminous with a sidewall of the first dielectric layer and with a sidewall of the processor device.
A method comprising:
- bonding a first memory device to a wafer, the wafer comprising a processor device, the first memory device comprising a first conductive via;
- forming a first dielectric layer around the first memory device;
- forming a second conductive via through the first dielectric layer, the second conductive via connected to the processor device, a top surface of the second conductive via being planar with a top surface of the first dielectric layer and a top surface of the first conductive via;
- and
- sawing the first dielectric layer and the wafer to singulate the processor device, a sidewall of the first dielectric layer being laterally coterminous with a sidewall of the processor device.
Dependencies are inferred from the claim text.