Semiconductor packages and method for fabricating the same

A semiconductor package comprising:

• a front side redistribution layer;
• a three-dimensional integrated circuit (3D IC) structure disposed on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die having through-silicon vias (TSVs) and a second semiconductor chip die disposed on the first semiconductor chip die, wherein the second semiconductor chip die is electrically coupled to the front side redistribution layer by the through-silicon vias (TSVs);
• a plurality of first connection members disposed between the first semiconductor chip die and the second semiconductor chip die to electrically couple the first semiconductor chip die to the second semiconductor chip die;
• a plurality of second connection members disposed between the first semiconductor chip die and the front side redistribution layer to electrically couple the first semiconductor chip die to the front side redistribution layer;
• an insulating member disposed between the first semiconductor chip die and the second semiconductor chip die to surround the plurality of first connection members;
• a plurality of conductive posts bonded to the front side redistribution layer and disposed side by side next to the 3D IC structure on the front side redistribution layer;
• a molding material disposed on the front side redistribution layer to encapsulate the first semiconductor chip die, the second semiconductor chip die, the insulating member, the plurality of second connection members, and the plurality of conductive posts;
• a back side redistribution layer disposed on the molding material and the plurality of conductive posts and bonded to the plurality of conductive posts;
• and
• a third semiconductor chip die disposed on the back side redistribution layer.

A method for fabricating a semiconductor package, comprising:

• forming a front side redistribution layer on a carrier;
• forming a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer,
• wherein the forming of the 3D IC structure comprises:
• mounting a first semiconductor chip die to the front side redistribution layer;
• and
• bonding a second semiconductor chip die to the first semiconductor chip die using a plurality of connection members, wherein the plurality of connection members are surrounded by an insulating member;
• encapsulating the first semiconductor chip die, the second semiconductor chip die, and the insulating member on the front side redistribution layer within a molding material;
• and
• forming a back side redistribution layer on the molding material.