Semiconductor packages and method for fabricating the same

A semiconductor package comprising:

• a front side redistribution layer including a plurality of first redistribution vias;
• a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs;
• a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure;
• a plurality of conductive fillers on the printed circuit board;
• a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure, the printed circuit board, and the plurality of conductive fillers;
• a back side redistribution layer on the molding material and including a plurality of second redistribution vias;
• and
• a third semiconductor chip die on the back side redistribution layer.

A method for fabricating a semiconductor package, the method comprising:

• forming a cavity in a printed circuit board;
• forming a three-dimensional integrated circuit (3D IC) structure inside the cavity, the 3D IC structure including a first semiconductor chip die on a second semiconductor chip die having through-silicon vias (TSVs);
• at least partially encapsulating the printed circuit board and the 3D IC structure with a molding material;
• forming a front side redistribution layer on a lower surface of the printed circuit board and a lower surface of the second semiconductor chip die, wherein the front side redistribution layer is electrically coupled with the first semiconductor chip die by the TSVs;
• and
• forming a back side redistribution layer on the molding material.