Wafer-level packaging method for semiconductor and semiconductor package

Abstract

Disclosed are a wafer-level packaging method for a semiconductor and a semiconductor package. The wafer-level packaging method for the semiconductor comprises: providing a first wafer having one or more memory chip units, each memory chip unit having a storage array circuit and a peripheral circuit, a first scribe line being provided between adjacent memory chip units; providing a second wafer having one or more logic chip units, an area of each logic chip unit corresponding to an area of N memory chip units, N being a natural number greater than or equal to one, a second scribe line being provided between adjacent logic chip units, the second scribe line matching the first scribe line at the periphery of the N memory chip units; and bonding the first wafer to the second wafer to enable the logic chip units to match with the N memory chip units correspondingly. The wafer-level packaging method for the semiconductor expands the application range of a package of a memory wafer.

Dependencies are inferred from the claim text.