Semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPei-Yu Wang, Yu-Xuan Huang
Life of this patent
Estimating the term…
Abstract
In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
Claims20
A device comprising:
- a first nanostructure;
- a gate structure wrapped around the first nanostructure;
- a first source/drain region adjacent the gate structure;
- a first dielectric layer over the first source/drain region;
- an interlayer dielectric over the first dielectric layer, a material of the interlayer dielectric being different than a material of the first dielectric layer;
- and
- a conductive line extending through the interlayer dielectric, the conductive line disposed over the first source/drain region, the conductive line isolated from the first source/drain region by the first dielectric layer, a top surface of the conductive line being coplanar with a top surface of the gate structure.
A device comprising:
- a back-side interconnect structure comprising a power rail;
- a front-side interconnect structure comprising a first interconnect;
- and
- a device layer between the back-side interconnect structure and the front-side interconnect structure, the device layer comprising:
- a transistor comprising a source/drain region;
- a power rail contact contacting a back-side of the source/drain region, the power rail connected to the power rail contact;
- a dielectric material completely covering a front-side of the source/drain region;
- and
- a conductive line on the dielectric material, the first interconnect connected to the conductive line.
A device comprising:
- a first dielectric layer;
- a nanostructure over the first dielectric layer;
- a gate structure wrapped around the nanostructure;
- a first spacer adjacent the gate structure;
- a first source/drain region adjacent the first spacer and the nanostructure;
- a second dielectric layer completely covering a front-side of the first source/drain region;
- and
- a power rail contact extending through the first dielectric layer, the power rail contact connected to a back-side of the first source/drain region.
Dependencies are inferred from the claim text.