3d integrated circuit (3dic) structure and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsChoongbin YIM, Jongkook KIM, Chengtar WU
Life of this patent
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Abstract
A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.
Claims20
A 3D integrated circuit structure, comprising:
- a redistribution layer structure;
- a first semiconductor chip die on the redistribution layer structure;
- a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die;
- a molding material surrounding the first semiconductor chip die and the plurality of core balls;
- an interconnection structure on the molding material;
- and
- a second semiconductor chip die on the interconnection structure,
- wherein a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.
A 3D integrated circuit structure, comprising:
- a first redistribution layer structure;
- a molding material on the first redistribution layer structure;
- an interconnection structure on the molding material;
- a first semiconductor chip die in the molding material and comprising a first surface and a second surface opposite the first surface, wherein the first surface is electrically coupled to the first redistribution layer structure and the second surface is electrically coupled to the interconnection structure;
- a plurality of core balls in the molding material and adjacent the first semiconductor chip die, wherein one portion of each core ball is electrically coupled to the first redistribution layer structure, and an opposite portion of each core ball is electrically coupled to the interconnection structure;
- and
- a second semiconductor chip die on the interconnection structure,
- wherein a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.
A method for manufacturing a 3D integrated circuit structure, the method comprising:
- forming a first redistribution layer structure;
- bonding a plurality of core balls on the first redistribution layer structure;
- mounting a first semiconductor chip die on the first redistribution layer structure;
- encapsulating the first semiconductor chip die and the plurality of core balls with molding material;
- and
- electrically coupling a second semiconductor chip die to the first semiconductor chip die and the plurality of core balls,
- wherein a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.
Dependencies are inferred from the claim text.