Semiconductor devices

A semiconductor device comprising:

• a substrate including an active region that extends in a first direction;
• a gate structure extending on the substrate in a second direction, wherein the second direction intersects the first direction;
• source/drain regions on the active region, wherein the source/drain regions are adjacent the gate structure;
• a vertical power structure extending through the substrate in a third direction that is perpendicular to an upper surface of the substrate, wherein the vertical power structure is electrically connected to at least a portion of the source/drain regions;
• a backside insulating layer on a lower surface of the substrate, wherein the backside insulating layer is in a periphery of the vertical power structure;
• an alignment insulating layer on a lower surface of the backside insulating layer, wherein the alignment insulating layer has an opening that exposes a lower surface of the vertical power structure;
• and
• a backside power structure that fills the opening and is connected to the vertical power structure,
• wherein the alignment insulating layer has a first thickness in a first region adjacent to the vertical power structure and a second thickness in a second region,
• wherein the second thickness is thicker than the first thickness, and
• wherein the second region is farther than the first region from the vertical power structure.

A semiconductor device comprising:

• a substrate including an active region that extends in a first direction;
• a gate structure extending on the substrate in a second direction, wherein the second direction intersects the first direction;
• source/drain regions on the active region, wherein the source/drain regions are adjacent the gate structure;
• a vertical power structure extending through the substrate in a third direction that is perpendicular to an upper surface of the substrate, wherein the vertical power structure is electrically connected to at least a portion of the source/drain regions;
• an alignment insulating layer on a lower surface of the substrate, wherein the alignment insulating layer has an opening that exposes a lower surface of the vertical power structure;
• and
• a backside power structure that fills the opening of the alignment insulating layer and is connected to the vertical power structure,
• wherein an upper surface of the vertical power structure is located on a level in the third direction, equal to or higher than levels of upper surfaces of the source/drain regions in the third direction relative to the substrate, and
• wherein a level of the lower surface of the vertical power structure in the third direction is lower than a level of the lower surface of the substrate in the third direction relative to the substrate.