Methods for correcting warpage with stress films and package structures thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Chieh HSIAO, Chih Hsin YANG, Dian-Hau CHEN
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Abstract
Embodiments of the present disclosure relate to methods for warpage correction. Particularly, embodiments of the present disclosure relate to substrate level warpage correction by depositing one or more warpage correction layers in a redistribution layer (RDL) structure, a front side warpage correction layer, and/or a back side warpage correction layer. In some embodiments, the warpage correction layer is a high stress dielectric layer. Characteristics of the warpage correction layer, such as stress level, and thickness, may be determined according to the substrate level warpage and the die level packaging scheme using an auto process control program.
Claims20
A method for correcting warpage, comprising:
- measuring a substrate level warpage prior to forming a RDL structure on a substrate;
- determining a difference between the measured warpage and a target warpage;
- and
- performing a substrate level warpage correction if the difference is greater than a tolerance, wherein the substrate level warpage correction includes at least one of:
- forming a warpage correction layer in the RDL structure;
- forming a front side warpage correction layer over the RDL structure;
- and
- forming a back side warpage correction layer.
A method for correcting warpage, comprising:
- determining a die level warpage tolerance according to a packaging scheme;
- determining a target substrate level warpage according to the die level warpage;
- measuring a substrate level warpage of a substrate having a device layer and an interconnect structure formed on a front side of the substrate;
- determining characteristics of a warpage correction layer according to the substrate level warpage;
- forming the warpage correction layer, wherein the warpage correction layer includes one of a stress dielectric layer in the RDL structure over the interconnect structure, a front side dielectric planar layer over the RDL layer, and a back side stress layer on a back side of the substrate;
- and
- dicing the substrate to individual dies.
A package structure, comprising:
- a first die structure, comprising:
- a first substrate;
- a first device layer formed over a front side of the first substrate;
- a first interconnect structure formed over the first device layer;
- a first RDL structure formed over the first interconnect structure;
- and
- a back side warpage correction film formed on a backside of the first substrate;
- and
- a second die structure bond to the first die structure, wherein the second die structure comprises:
- a second substrate;
- a second device layer formed over a front side of the second substrate;
- a second interconnect structure formed over the second device layer;
- and
- a second RDL structure formed over the second interconnect structure.
Dependencies are inferred from the claim text.