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US 2024/0258168 A1Published application
Self Aligned Contact Scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYu-Lien Huang
Life of this patent
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Abstract
A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
Claims20
A device comprising:
- a gate structure comprising a gate dielectric, a gate electrode, and a first gate spacer and a second gate spacer disposed on opposing sides of the gate electrode;
- a first hard mask layer over the gate electrode and the gate dielectric;
- a second hard mask layer disposed over the first gate spacer, the second hard mask layer being a different material than a material of the first hard mask layer, the second hard mask layer and the first hard mask layer contacting the first gate spacer;
- and
- a conductive feature adjacent the first gate spacer.
2 more elements
A device comprising:
- a gate structure, wherein the gate structure comprises a gate electrode over a gate dielectric, and a first gate spacer and a second gate spacer disposed on either side of the gate electrode;
- a first source/drain and a second source/drain on opposing sides of the gate structure;
- a first etch stop layer on a sidewall of the gate structure;
- a first hard mask over the gate electrode;
- and
- a second hard mask over the first etch stop layer.
3 more elements
A device comprising:
- a gate structure over a channel region, the gate structure comprising a gate electrode, a gate mask over the gate electrode, and a first gate spacer and a second gate spacer on opposing sides of the gate electrode, and
- a first source/drain and a second source/drain on opposing sides of the gate structure;
- a first dielectric layer over a sidewall of the first gate spacer and on an upper surface of the first source/drain, the first gate spacer being between the first dielectric layer and the gate electrode;
- a second dielectric layer over a sidewall of the second gate spacer and on an upper surface of the second source/drain, the second gate spacer being between the second dielectric layer and the gate electrode;
- a third dielectric layer adjacent the second dielectric layer, the second dielectric layer being between the third dielectric layer and the second gate spacer;
- a first hard mask over the first gate spacer and the first dielectric layer;
- and
- a second hard mask over the second gate spacer and the second dielectric layer, wherein the first hard mask and second hard mask have upper surfaces level with an upper surface of the third dielectric layer.
5 more elements
Dependencies are inferred from the claim text.