Selective deposition for integrated circuit interconnect structures

A method, comprising:

• receiving a workpiece that includes a substrate and an interconnect structure disposed on the substrate, wherein the interconnect structure includes a first conductive feature disposed within a first dielectric layer;
• wherein the wherein the first conductive feature includes a liner interfacing the first dielectric layer, a fill material over the liner and spaced apart from the first dielectric layer by the liner, and a line cap disposed on the liner and the fill material,
• selectively forming a catalyst layer over the first dielectric layer without forming the catalyst layer over the line cap;
• selectively forming an alignment feature on the catalyst layer;
• after the selectively forming of the alignment feature, depositing an etch stop layer over the alignment feature and the line cap;
• and
• depositing a second dielectric layer over the etch stop layer.

A method, comprising:

• receiving a workpiece that includes a first conductive line disposed within a first dielectric layer;
• performing a surface treatment to the first conductive line;
• after the surface treatment, selectively forming a blocking layer on the first conductive line;
• after the selectively forming of the blocking layer, selectively forming a catalyst layer on the first dielectric layer;
• selectively forming an alignment feature on the catalyst layer
• after the selectively forming of the alignment feature, removing the blocking layer;
• after the removing of the blocking layer, conformally depositing an etch stop layer over the catalyst layer, the alignment feature, and the first conductive line;
• and
• depositing a second dielectric layer over the etch stop layer.