Compute optimization mechanism for deep neural networks

A graphics processing apparatus comprising:

• an interconnect to a host processor;
• and
• a plurality of graphics processing clusters, each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via an interconnect, a graphics processing cluster of the plurality of graphics processing clusters including:
• a register file to store a plurality of different types of operands;
• a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file;
• and
• a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file, the second number of registers different from the first number of registers.

A method comprising:

• storing operands for a plurality of different types of operations to a register file of a graphics processing including a plurality of graphics processing clusters, each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via an interconnect;
• processing a first number of threads having operands stored in a first number of registers of the register file via a first plurality of processing resources of a first type;
• and
• processing second number of threads having operands stored in a second number of registers of the register file via a second plurality of processing resources of a second type, the second number of registers different from the first number of registers.

A graphics processing system comprising:

• an interconnect to a host processor;
• a memory device coupled with the interconnect;
• and
• a graphics processor coupled with the interconnect and the memory device, the graphics processor including a plurality of graphics processing clusters, each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via an interconnect, a graphics processing cluster of the plurality of graphics processing clusters including:
• a register file to store a plurality of different types of operands;
• a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file;
• and
• a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file, the second number of registers different from the first number of registers.