Method and system for use with an electronic design automation (eda) tool to optimize clock scheduling

A computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling to reduce logic circuit area, said system comprising:

• a processor;
• and,
• a memory, said memory containing instructions which, when executed by said processor, are operative to:
• determine an initial timing and area optimized design for a logic circuit;
• determine an optimal set of clock anchor points (CAPs) on a clock tree for said logic circuit;
• determine slack statistics for a plurality of elements in said logic circuit;
• schedule clock skews for said CAPs associated with said plurality of elements as a function of said slack statistics;
• generate a refined timing and area optimized design for said logic circuit based on said clock skews;
• and,
• utilize said refined timing and area optimized design as input to a clock tree synthesis module of said EDA tool.