Rail power density aware standard cell placement for integrated circuits

A system, comprising:

• a memory that stores power density values for a plurality of cells in an initial cell placement for an integrated circuit layout, wherein the initial cell placement is subdivided into multiple regions, and wherein at least a first region of the multiple regions includes multiple power supply rails and a first portion of the cells of the plurality of cells in the initial cell placement;
• and
• a processor that is connected to the memory, wherein the processor is configured to:
• compute a per-rail power density value for each power supply rail within the first region based on the power density values of the first portion of the cells;
• for each of a plurality of cell placements of the first portion of the cells, evaluate an objective function based on the per-rail power density values to generate a result value;
• and
• select a cell placement of the plurality of cell placements associated with a minimum result value compared with the result values for other cell placements in the plurality of cell placements.

A non-transitory computer-readable media storing computer instructions for producing an integrated circuit layout that, when executed by one or more processors, cause the one or more processors to perform the steps of:

• obtaining power density values for a plurality of cells in an initial cell placement for an integrated circuit layout, wherein the initial cell placement is subdivided into multiple regions, and wherein at least a first region of the multiple regions includes multiple power supply rails and a first portion of the cells of the plurality of cells in the initial cell placement;
• computing a per-rail power density value for each power supply rail within the first region based on the power density values of the first portion of the cells;
• for each of a plurality of cell placements of the first portion of the cells, evaluating an objective function based on the per-rail power density values to generate a result value;
• and
• selecting a cell placement of the plurality of cell placements associated with a minimum result value compared with the result values for other cell placements in the plurality of cell placements.

A computer-implemented method, comprising:

• obtaining power density values for a plurality of cells in an initial cell placement for an integrated circuit layout, wherein the initial cell placement is subdivided into multiple regions, and wherein at least a first region of the multiple regions includes multiple power supply rails and a first portion of the cells of the plurality of cells in the initial cell placement;
• computing a per-rail power density value for each power supply rail within the first region based on the power density values of the first portion of the cells, wherein at least one cell in the first portion of the cells has a fixed placement within the first region;
• for each of a plurality of cell placements of the first portion of the cells, evaluating an objective function based on the per-rail power density values to generate a result value;
• and
• selecting a cell placement of the plurality of cell placements, in response to the result values.