Interconnect for direct memory access controllers
AssigneeMicrosoft Technology Licensing, LLC
InventorsRuihua PENG, Monica Man Kay TANG, Xiaoling XU
Life of this patent
Estimating the term…
Abstract
A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.
Claims20
An integrated circuit comprising:
- a plurality of direct memory access (DMA) controllers;
- and
- an on-chip interconnect configured to implement control logic to:
- convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request indicates one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers;
- and
- broadcast or multi-cast a read response by conveying respective copies of the read response from the source memory device to the primary DMA controller and the one or more secondary DMA controllers, each of the primary DMA controller and one or more secondary DMA controllers having a corresponding on-chip destination memory device included in the integrated circuit,
- wherein the primary DMA controller and the one or more secondary DMA controllers are each configured to write data included in the read response to the corresponding on-chip destination memory devices for the respective primary and secondary DMA controllers.
A method for use with an integrated circuit that includes a plurality of direct memory access (DMA) controllers and an on-chip interconnect, the method comprising implementing control logic at the on-chip interconnect at least in part by:
- conveying a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request indicates one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers;
- broadcasting or multi-cast a read response by conveying respective copies of the read response from the source memory device to the primary DMA controller and the one or more secondary DMA controllers, each of the primary DMA controller and one or more secondary DMA controllers having a corresponding on-chip destination memory device included in the integrated circuit;
- and
- at the primary DMA controller and the one or more secondary DMA controllers, writing data included in the read response to the corresponding on-chip destination memory devices for the respective primary and secondary DMA controllers.
An integrated circuit comprising:
- a plurality of direct memory access (DMA) controllers;
- and
- an on-chip interconnect configured to implement control logic to:
- convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device, wherein the read request includes:
- a header including a response recipient indicator specifying one or more secondary DMA controllers that form a proper subset of the plurality of DMA controllers;
- and
- a source memory access location;
- and
- broadcast or multi-cast a read response by conveying respective copies of the read response from the source memory device to the primary DMA controller and the one or more secondary DMA controllers, each of the primary DMA controller and one or more secondary DMA controllers having a corresponding on-chip destination memory device included in the integrated circuit,
- wherein:
- the primary DMA controller and the one or more secondary DMA controllers are each configured to write a read response payload included in the read response to the corresponding on-chip destination memory devices for the respective primary and secondary DMA controllers;
- and
- the read response payload is located at the source memory access location indicated in the read request.
Dependencies are inferred from the claim text.