Memory system performing cache bypassing operation and cache management method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsShinhaeng Kang, Suk Han Lee, Kyomin Sohn
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AssigneeSamsung Electronics Co., Ltd.
InventorsShinhaeng Kang, Suk Han Lee, Kyomin Sohn
Estimating the term…
Disclosed is a semiconductor memory device and a memory system, including at least one high-bandwidth memory device configured to store data or output stored data according to an access command, a processor configured to generate the access command for the high-bandwidth memory device, and a logic die on the high-bandwidth memory device and including a last level cache providing a cache function to the processor. The last level cache is configured to perform a cache bypassing operation to directly access the high-bandwidth memory device without a cache replacement operation when an invalid line and a clean line do not exist in a cache miss state in response to a cache read or cache write request by the processor.
A memory system, comprising:
A method for managing a cache memory included in a buffer die of a high-bandwidth memory, the method comprising:
A memory system, comprising:
Dependencies are inferred from the claim text.