In-order processor using multiple-issue scheme and method of operating the same

A method of operating a processor using a multiple-issue scheme, the method comprising:

• fetching a plurality of instructions together in a fetching stage;
• determining whether to multiple-issue the plurality of fetched instructions in a pre-decoding stage;
• decoding an issued instruction based on the determination in a decoding stage, wherein
• a stall of the decoded instruction is caused by a data hazard;
• and
• executing the issued instruction transmitted in the decoded stage in an execution stage,
• wherein
• the processor comprises:
• a buffer configured to store stall history information on the plurality of multiple-issued instructions when the plurality of multiple-issued instructions are stalled by the data hazard, and
• the pre-decoding stage is a stage of determining whether to multiple-issue the plurality of fetched instructions, based on the stall history information of the buffer.