Technique for improving efficiency of data processing operations in an apparatus that employs register renaming

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• execution circuitry to execute instructions in order to perform data processing operations specified by those instructions;
• a plurality of registers to store data values for access by the execution circuitry when performing the data processing operations, each register having an associated physical register identifier;
• register rename circuitry to select physical register identifiers to associate with architectural register identifiers specified by the instructions;
• and
• rename storage having a plurality of entries, each entry being associated with one of the architectural register identifiers and used by the register rename circuitry to indicate a physical register identifier selected for association with that one of the architectural register identifiers;
• the register rename circuitry comprising an execute unit, and being responsive to detection of an early execute condition for a given instruction, the early execute condition requiring at least detection that each source value required to execute the given instruction is available to the register rename circuitry without accessing the plurality of registers, to cause the execute unit to perform the data processing operation specified by the given instruction in order to generate a result value, and to cause the generated result value to be stored in an entry of the rename storage associated with a destination architectural register identifier specified by the given instruction.

A method comprising:

• detecting an early execute condition for a given instruction, the early execute condition requiring at least detection that each source value required to execute the given instruction is available to register rename circuitry without accessing registers storing data values for access by execution circuitry when performing data processing operations specified by instructions;
• and
• in response to detecting the early execute condition for the given instruction:
• performing, by an execute unit included in the register rename circuitry, a data processing operation specified by the given instruction in order to generate a result value, and writing the generated result value in an entry of rename storage, the entry being associated with a destination architectural register identifier specified by the given instruction, the rename storage comprising a plurality of entries, each entry being associated with one architectural register identifier specified by the instructions and capable of being used to indicate a physical register identifier selected for association with that one architectural register identifier.