Hierarchical compiling and execution in a machine learning hardware accelerator
AssigneeGoogle Inc.
InventorsJohn Navil Joseph, Jack Liu, Dong Hyuk Woo, Jing Pu
Life of this patent
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AssigneeGoogle Inc.
InventorsJohn Navil Joseph, Jack Liu, Dong Hyuk Woo, Jing Pu
Estimating the term…
This disclosure describes a system and method for compiling and executing machine learning inferences in an array of multi-core computing devices. Each multi-core computing device can be an application specific integrated circuit (ASIC) or group of ASICS. In many applications, the array of computing devices changes from inference to inference, and can be adjusted based on the requirements of the inference. Additionally, each ASIC can have multiple processing cores, and multiple types of processing cores. Therefore, performing optimizations and scheduling at compile time, can dramatically increase the efficiency of the array in executing the inference. In some implementations, it is possible to select an amount of time or effort to be spent optimizing during compiling, giving the user flexibility in determining whether to spend time during compilation or during execution.
A method for distributing executable jobs in an array of multi-core computing devices, comprising:
A non-transitory computer-readable storage medium coupled to one or more processors and having instructions stored thereon which, when executed by the one or more processors, cause the one or more processors to perform operations for distributing executable jobs in an array of multi-core computing devices, the operations comprising:
A system, comprising:
21-38. (canceled)
Dependencies are inferred from the claim text.