Feedback for multi-level signaling in a memory device

A dynamic random-access memory (DRAM) device, comprising:

• a receiver of a decision feedback equalization (DFE) circuit coupled with a Data In or Out (DQ) channel and configured to receive a signal, the receiver comprising a multi-phase architecture, and the receiver comprising:
• a first slicer circuit configured to determine a voltage level at a first clock phase of the signal;
• a first feedback circuit coupled with an input of a second slicer circuit and an output of the first slicer circuit, the first feedback circuit configured to receive a first feedback signal from the first slicer circuit and modify the signal input into the second slicer circuit based at least in part on a first parameter associated with a first mode register of the DRAM device;
• the second slicer circuit configured to determine a voltage level at a second clock phase of the signal;
• a second feedback circuit coupled with an input of a third slicer circuit and an output of the second slicer circuit, the second feedback circuit configured to receive a second feedback signal from the second slicer circuit and modify the signal input into the third slicer circuit based at least in part on a second parameter associated with a second mode register of the DRAM device;
• and
• the third slicer circuit configured to determine a voltage level at a third clock phase of the signal.

A method, comprising:

• reducing, using an amplifier associated with a decision feedback equalization (DFE) circuit of a dynamic random-access memory (DRAM) device coupled with a Data In or Out (DQ) channel of the DRAM device, inter-symbol interference between a first clock phase of a signal a second clock phase of the signal, and a third clock phase of the signal;
• determining, by a first slicer circuit of the DFE circuit, a voltage level of the signal that occurs at the first clock phase based at least in part on reducing the inter-symbol interference;
• modifying, by a first feedback circuit coupled with an input of a second slicer circuit and an output of the first slicer circuit, a first feedback signal sent to a second circuit based at least in part on a first parameter associated with a first mode register of the DRAM device;
• determining, by the second slicer circuit, a voltage level of the signal that occurs at the second clock phase based at least in part on the first feedback signal;
• modifying, by a second feedback circuit, a second feedback signal sent to a third slicer circuit based at least in part on a second parameter associated with a second mode register of the DRAM device;
• and
• determining, by the third slicer circuit, a voltage level of the signal that occurs at a third clock phase based at least in part on the second feedback signal.

An apparatus, comprising:

• a dynamic random-access memory (DRAM) device coupled with a Data In or Out (DQ) channel of the DRAM device;
• and
• processing circuitry coupled with the DRAM device and configured to cause the apparatus to:
• reduce, using an amplifier associated with a decision feedback equalization (DFE) circuit of the DRAM device, inter-symbol interference between a first clock phase of a signal a second clock phase of the signal, and a third clock phase of the signal;
• determining, by a first slicer circuit of the DFE circuit, a voltage level of the signal that occurs at the first clock phase based at least in part on reducing the inter-symbol interference;
• modifying, by a first feedback circuit coupled with an input of a second slicer circuit and an output of the first slicer circuit, a first feedback signal sent to a second circuit based at least in part on a first parameter associated with a first mode register of the DRAM device;
• determining, by the second slicer circuit, a voltage level of the signal that occurs at the second clock phase based at least in part on the first feedback signal;
• modifying, by a second feedback circuit, a second feedback signal sent to a third slicer circuit based at least in part on a second parameter associated with a second mode register of the DRAM device;
• and
• determining, by the third slicer circuit, a voltage level of the signal that occurs at a third clock phase based at least in part on the second feedback signal.