Adaptive Cache Management System and Method
AssigneeDell Products L.P.
InventorsVladimir Shveidel, Lior Kamran, Amitai Alkalay
Life of this patent
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Abstract
A method, computer program product, and computing system for identifying a cache probe event associated with a cache memory system. A cache size of the cache memory system may be adjusted based upon, at least in part, the cache probe event. A cache size adjustment impact may be determined based upon, at least in part, a change in a hit rate associated with the cache memory system. It may be determined whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact.
Claims20
A computer-implemented method, executed on a computing device, comprising:
- identifying a cache probe event associated with a cache memory system;
- adjusting a cache size of the cache memory system based upon, at least in part, the cache probe event;
- determining a cache size adjustment impact based upon, at least in part, a change in a hit rate associated with the cache memory system;
- and
- determining whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact.
A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
- identifying a cache probe event associated with a cache memory system;
- adjusting a cache size of the cache memory system based upon, at least in part, the cache probe event;
- determining a cache size adjustment impact based upon, at least in part, a change in a hit rate associated with the cache memory system;
- and
- determining whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact.
A computing system comprising:
- a memory;
- and
- a processor configured to identify a cache probe event associated with a cache memory system, wherein the processor is further configured to adjust a cache size of the cache memory system based upon, at least in part, the cache probe event, wherein the processor is further configured to determine a cache size adjustment impact based upon, at least in part, a change in a hit rate associated with the cache memory system, and wherein the processor is further configured to determine whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact.
Dependencies are inferred from the claim text.