Memory management method to save energy
AssigneeSTMicroelectronics International N.V.
InventorMichael GIOVANNINI
Life of this patent
Estimating the term…
Abstract
A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.
Claims15
A system, comprising:
- a memory that includes a plurality of memory units accessible in write mode and in read mode;
- wherein each memory unit comprises an array of memory cells and a peripheral circuit of access to said array of memory cells;
- wherein each memory unit is configurable for operation in a first operating mode and a second operating mode;
- wherein, in the first operating mode and the second operating mode, the array of memory cells are configured to retain data until a subsequent powering off of the memory unit;
- wherein in the first operating mode the peripheral circuit is powered and wherein in the second operating mode the peripheral circuit is not powered;
- and
- a controller configured to control any memory unit of the memory which has undergone no write or read access for a determined time period to be in the second operating mode.
A method of controlling a memory that includes a plurality of memory units accessible in write mode and in read mode, each memory unit including an array of memory cells and a peripheral circuit of access to said array of memory cells, the method comprising:
- configuring the array of memory cells, in the first operating mode and the second operating mode, to retain data until a subsequent powering off of the memory unit;
- powering the peripheral circuit in the first operating mode;
- not powering the peripheral circuit in the second operating mode;
- and
- configuring any memory unit of the memory having undergone no write or read access beyond a determined time period to be in the second operating mode.
A system, comprising:
- a memory including a plurality of memory units accessible in write mode and in read mode;
- wherein each memory unit comprises an array of memory cells and a peripheral circuit of access to said array of memory cells;
- a controller including a timer for each memory unit and a control register for each memory unit;
- wherein the peripheral circuit is powered when the corresponding control register stores a first control value associated with a first operating mode and is not powered when the corresponding control register stores a second control value associated with a second operating mode;
- wherein the array of memory cells is powered in both the first operating mode and the second operating mode;
- and
- wherein the controller is configured to use the timer associated with each memory unit to determine whether a time period in excess of a threshold has elapsed since a last write or read access to the array of memory cells within the corresponding memory unit has occurred, and in response thereto to switch the control register for that corresponding memory unit from the first control value to the second control value to change operation of that corresponding memory unit from the first operating mode to the second operating mode.
Dependencies are inferred from the claim text.