Memory page access instrumentation
AssigneeNVIDIA Corporation
InventorsNiladrish Chatterjee, Zachary Joseph Susskind, Donghyuk Lee, James Michael O'Connor
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Abstract
Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.
Claims20
A method, comprising:
- distributing execution of a program to multiple processing units, wherein each processing unit is directly coupled to a local memory of a memory system and indirectly coupled to the local memories that are directly coupled to the remaining processing units;
- launching a first portion of the program for execution as a first thread array by a first processing unit of the processing units, wherein pages of the memory system are assigned to a set of counters;
- for accesses of the memory system during execution of the first thread array, updating the counter associated with the page specified by the access;
- and
- in response to completion of execution of the first thread array, reading at least a portion of the set of counters to produce a memory access profile for the first thread array.
A system, comprising:
- a memory system;
- and
- a processor comprising multiple processing units, wherein the processor is configured to produce a memory access profile by:
- distributing execution of a program to the multiple processing units, wherein each processing unit is directly coupled to a local memory of the memory system and indirectly coupled to the local memories that are directly coupled to the remaining processing units;
- launching a first portion of the program for execution as a first thread array by a first processing unit of the processing units, wherein pages of the memory system are assigned to a set of counters;
- for accesses of the memory system during execution of the first thread array, updating the counter associated with the page specified by the access;
- and
- in response to completion of execution of the first thread array, reading at least a portion of the set of counters to produce the memory access profile for the first thread array.
Dependencies are inferred from the claim text.