Concurrently writing less-densely-programmed and more-densely-programmed memory without additional hardware

A method comprising:

• receiving, by a memory device, a first command to program a first set of memory cells of a first array of memory cells with a first logical state, wherein the first array is configured with a first density and comprises one or more first planes;
• receiving, by the memory device, a second command to program a second set of memory cells of a second array of memory cells with a second logical state corresponding in threshold voltage range to the first logical state, wherein the second array is configured with a second density that is less than the first density and comprises one or more second planes, and wherein the first set of memory cells and the second set of memory cells are associated with a shared wordline;
• and
• causing, by control logic of the memory device, the first set of memory cells and the second set of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

A memory device comprising:

• a first array of memory cells configured as one of quad-level cell (QLC) memory or penta-level cell (PLC) memory and comprising one or more first planes;
• a second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array comprising one or more second planes;
• a single set of charge pumps coupled with the first array and the second array;
• and
• control logic operatively coupled with the first array, the second array, and the single set of charge pumps, wherein the control logic is to perform operations comprising:
• receiving a first command to program a first set of memory cells of the first array with a first logical state;
• receiving a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state, wherein the first set of memory cells and the second set of memory cells are associated with a shared wordline;
• and
• causing the single set of charge pumps to concurrently program the first set of memory cells and the second set of memory cells with a threshold voltage distribution corresponding to the first logical state.