Data buffer for memory devices with unidirectional ports

A data buffer device comprising:

• command scheduling logic to generate memory device commands for writing to and reading from a memory device based on command packets from a memory controller, the memory device commands including at least activate commands, read commands, and write commands, and the command scheduling logic to control order and timing of outputting the memory device commands to the memory device, outputting write data to the memory device, and receiving read data from the memory device according to timing specifications of the memory device;
• a host side interface to receive the command packets and the write data from the memory controller and to transmit the read data to the memory controller;
• and
• a memory side interface to transmit the memory device commands and the write data to the memory device and to receive the read data from the memory device.

A memory module comprising:

• a first set of memory devices including at least a first memory device;
• and
• a first data buffer device comprising:
• command scheduling logic to generate memory device commands for writing to and reading from the first memory device based on command packets from a memory controller, the memory device commands including at least activate commands, read commands, and write commands, and the command scheduling logic to control order and timing of outputting the memory device commands to the first memory device, outputting write data to the first memory device, and receiving read data from the first memory device according to timing specifications of the first memory device;
• a host side interface to receive the command packets and the write data from the memory controller and to transmit the read data to the memory controller;
• and
• a memory side interface to transmit the memory device commands and the write data to the first memory device and to receive the read data from the first memory device;
• and
• first communication lines coupling the first memory device and the memory side interface of the first data buffer device.

A method for operating a data buffer device, the method comprising:

• receiving, at a host side interface of the data buffer device, a host-side input packet for performing a memory operation;
• generating, by command scheduling logic of the data buffer device, an activate command for activating an address of a memory device associated with the memory operation of the host-side input packet;
• transmitting, by a memory side interface of the data buffer device, the activate command to the memory device;
• generating, by the command scheduling logic of the data buffer device, a memory device command for performing the memory operation associated with the host-side input packet;
• and
• transmitting, by the memory side interface of the data buffer device, the memory device command to the memory device at a scheduled time following the activate command.