Tiling Display Apparatus
AssigneeLG Display Co., Ltd.
InventorsSang Woo Park, Tae Gung Kim
Life of this patent
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Abstract
A tiling display apparatus includes a plurality of display modules connected to one another through a first interface circuit and a second interface circuit and a set board receiving a defect occurrence and position signal, generated in a broken-down module of the plurality of display modules, from the broken module through the first interface circuit in a first period, generating a defect recognition completion signal in a second period succeeding the first period, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit in the second period.
Claims12
A tiling display apparatus comprising:
- a plurality of display modules connected to one another through a first interface circuit and a second interface circuit;
- and
- a set board receiving a defect occurrence and position signal, generated in a broken-down module of the plurality of display modules, from the broken-down module through the first interface circuit in a first period, generating a defect recognition completion signal in a second period succeeding the first period, and transferring the defect recognition completion signal to the broken-down module through the second interface circuit in the second period,
- wherein each of the defect occurrence and position signal and the defect recognition completion signal is a pulse signal which swings between a high logic voltage and a low logic voltage.
A tiling display apparatus comprising:
- a set board;
- and
- a plurality of display modules connected to one another through a first interface circuit and a second interface circuit,
- wherein each of the plurality of display modules comprises:
- a timing controller configured to:
- generate, when the display module is broken-down, a defect occurrence and position signal, and transfer the defect occurrence and position signal to the set board through the first interface circuit in a first period, and receive a defect recognition completion signal, which is generated by the set board, through the second interface circuit in a second period succeeding the first period,
- wherein each of the defect occurrence and position signal and the defect recognition completion signal is a pulse signal which swings between a high logic voltage and a low logic voltage.
Dependencies are inferred from the claim text.