Device Disaggregation For Improved Performance
AssigneeAdeia Semiconductor Inc.
InventorsJavier A. DeLaCruz, Don Draper, Jung Ko, Steven L. Teig
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Abstract
The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.
Claims21
-20. (canceled)
A microelectronic device comprising:
- a plurality of dies, each die of the plurality of dies comprising one or more circuit elements;
- and
- a wafer directly hybrid-bonded to the plurality of dies, wherein:
- the wafer comprises one or more routing layers;
- each die of the plurality of dies is fabricated in a first process node;
- at least a portion of the wafer is fabricated in a second process node, the first process node being a more advanced node than the second process node;
- and
- at least some of the one or more routing layers communicatively couple a circuit element of one die of the plurality of dies to another circuit element of another die of the plurality of dies through interconnections formed by direct hybrid bonds between the wafer and the plurality of dies.
A microelectronic device comprising:
- one or more dies comprising active circuitry, the active circuitry comprising a plurality of circuit elements among the one or more dies;
- and
- a wafer directly hybrid-bonded to the one or more dies, the wafer comprising one or more routing layers, wherein:
- the one or more dies are fabricated in a first process node;
- at least a portion of the wafer is fabricated in a second process node, the first process node being a more advanced node than the second process node;
- and
- at least some of the one or more routing layers communicatively couple at least some of the plurality of circuit elements to one another through interconnections formed by direct hybrid bonds between the wafer and the one or more dies.
Dependencies are inferred from the claim text.