Memory device and method
OwnerJe-Min Hung, Win-San Khwa +1inventors
InventorsJe-Min Hung, Win-San Khwa, Meng-Fan Chang
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Abstract
An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time to digital convertor converts a time associated with the output voltage to a digital value.
Claims20
A memory device, comprising:
- a memory array comprising a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines;
- an Input/Output circuit connectable to a bitline of the plurality of bitlines of the memory array, wherein the I/O circuit comprises:
- a charge integration circuit coupled to the bitline,
- a comparator coupled to the charge integration circuit, and
- a time-to-digital converter coupled to the comparator, wherein the I/O circuit senses a multiply-accumulate value for the bitline in a time domain.
A method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising:
- sensing a voltage of a bitline;
- charging, by a charge integration circuit, a sensing node based on a decrease of the voltage on the bitline;
- comparing, by a comparator coupled to the charge integration circuit, a sensing voltage of the sensing node with a reference voltage;
- providing, by the comparator, an output voltage based on the comparison;
- and
- converting, by a time-to-digital converter coupled to the comparator, a time associated with the output voltage to a MAC value.
A method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising:
- selecting a multiplexer of a plurality of multiplexers of a memory device, wherein each of the plurality of multiplexers is associated with a predetermined number of bitlines of the plurality of bitlines;
- connecting, by the multiplexer, a bitline of the predetermined number of bitlines associated with the multiplexer to an associated Input/Output circuit;
- and
- sensing, by the Input/Output circuit, a multiply-accumulate value for the bitline in a time domain.
Dependencies are inferred from the claim text.