Back to results
US 2024/0215217 A1Published application
Vertical heterostructure semiconductor memory cell and methods for making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGerben DOORNBOS, Marcus Johannes Henricus VAN DAL
Life of this patent
Estimating the term…
Abstract
A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.
Claims20
A memory cell, comprising:
- a transistor including a source region, channel region and drain region in a nanowire structure;
- and
- a capacitive device on the transistor and including a first conductor in the nanowire structure.
A method of forming a memory cell, the method comprising:
- forming a source region, channel region and drain region of a transistor in a nanowire structure;
- and
- forming a first conductor of a capacitive device on the source region, channel region and drain region in the nanowire structure.
A memory device, comprising:
- a plurality of bit lines and plurality of word lines;
- and
- a plurality of memory cells at intersections of the plurality of bit lines and the plurality of word lines, comprising:
- a transistor including a source region, channel region and drain region in a nanowire structure;
- and
- a capacitive device on the transistor and including a first conductor in the nanowire structure.
3 more elements
Dependencies are inferred from the claim text.