US 2024/0213971 A1Published application

Comparator circuit with dynamic hysteresis

AssigneeTexas Instruments Incorporated

InventorHo-Young Lee

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Abstract

A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source/drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source/drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.

Claims20

Dependent claims

A comparator circuit, comprising:

a common source branch comprising:
first and second transistors having sources coupled in common to a supply terminal, the first transistor having a gate coupled to a first input of the comparator circuit, the second transistor having a gate coupled to a second input of the comparator circuit and a drain coupled to a first intermediate output, and the first transistor having a drain coupled to a second intermediate output;
a common gate branch, comprising:
third and fourth transistors having gates coupled in common to a first bias voltage, the third transistor having a source coupled to the first intermediate output and to a common terminal, and having a drain coupled to a third intermediate output, and the fourth transistor having a source coupled to the second intermediate output and the common terminal, and having a drain;
and
a bias circuit, coupled to a supply terminal and to the drain of the fourth transistor;
a digital output circuit, having an input coupled to the third intermediate output, and configured to present complementary logic levels at first and second outputs responsive to a voltage at its input;
and
a hysteresis branch, comprising:
a hysteresis current generator;
a first hysteresis transistor having a source-drain path coupled between an output of the hysteresis current generator and the second intermediate output, and having a gate coupled to the first output of the digital output circuit;
a second hysteresis transistor having a source-drain path coupled between the output of the hysteresis current generator and the first intermediate output, and having a gate coupled to the second output of the digital output circuit;
wherein the hysteresis current generator comprises:
first and second replica transistors having sources coupled in common to a first current source, and having drains coupled in common, the first replica transistor having a gate coupled to the first input, and the second replica transistor having a gate coupled to the second input;
a hysteresis capacitor coupled between the sources of the first and second replica transistors and the common terminal;
and
a first current mirror having a first leg coupled to the drains of the first and second replica transistors, and having a second leg coupled to a second current source;
and
a second current mirror having a first leg coupled to the second current source, and having a second leg;
and
an output transistor coupled to the second leg of the second current mirror, and coupled to the source/drain paths of the first and second hysteresis transistors.

18 more elements

A comparator circuit, comprising:

a common source branch comprising:
first and second transistors having sources coupled in common to a supply terminal, the first transistor having a gate coupled to a first input of the comparator circuit, the second transistor having a gate coupled to a second input of the comparator circuit and a drain coupled to a first intermediate output, and the first transistor having a drain coupled to a second intermediate output;
a common gate branch, comprising:
third and fourth transistors having gates coupled in common to a first bias voltage, the third transistor having a source coupled to the first intermediate output and to a common terminal, and having a drain coupled to a third intermediate output, and the fourth transistor having a source coupled to the second intermediate output and the common terminal, and having a drain;
and
a bias circuit, coupled to a supply terminal and to the drain of the fourth transistor;
a digital output circuit, having an input coupled to the third intermediate output, and configured to present complementary logic levels at first and second outputs responsive to a voltage at its input;
and
a hysteresis branch, comprising:
a hysteresis current generator;
a first hysteresis transistor having a source-drain path coupled between an output of the hysteresis current generator and the second intermediate output, and having a gate coupled to the first output of the digital output circuit;
a second hysteresis transistor having a source-drain path coupled between the output of the hysteresis current generator and the first intermediate output, and having a gate coupled to the second output of the digital output circuit;
wherein the hysteresis current generator comprises:
a first coupling capacitor coupled to the first input;
a second coupling capacitor coupled to the second input;
a current mirror comprising:
a first leg including a first leg transistor having a source coupled to a supply terminal, a drain coupled to a first current source, and a gate coupled to its drain;
a resistor coupled to the gate of the first leg transistor;
and
a second leg including a second leg transistor having a source coupled to a supply terminal, a gate coupled to the first and second coupling capacitors and coupled through the resistor to the gate of the first leg transistor, and a drain coupled to the source/drain paths of the first and second hysteresis transistors.

17 more elements

A comparator circuit, comprising:

a common source branch configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs;
a common gate branch configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs;
a digital output circuit, having an input coupled to the third intermediate output, and configured to present complementary logic levels at first and second outputs responsive to a voltage at its input;
and
a hysteresis branch, comprising:
a hysteresis current generator, comprising:
first and second replica transistors having source/drain paths coupled in parallel to a current source, the first replica transistor having a gate coupled to the first input, and the second replica transistor having a gate coupled to the second input;
and
a hysteresis capacitor coupled between the sources of the first and second replica transistors and the common terminal;
and
current mirror circuitry, coupled to the source/drain paths of the first and second replica transistors, and configured to supply a current at an output of the hysteresis current generator while the first and second replica transistors are substantially in an off state;
a first hysteresis transistor having a source-drain path coupled between the output of the hysteresis current generator and the second intermediate output, and having a gate coupled to the first output of the digital output circuit;
a second hysteresis transistor having a source-drain path coupled between the output of the hysteresis current generator and the first intermediate output, and having a gate coupled to the second output of the digital output circuit.

10 more elements

Dependencies are inferred from the claim text.