Self-biased amplifier circuit and a method for controlling a self-biased amplifier circuit

A method for controlling a self-biased amplifier circuit, said method comprising:

• receiving a differential input signal at an input of the self-biased amplifier circuit, wherein the input comprises a first and a second input node for receiving a first input signal and a second input signal forming the differential input signal, wherein the input comprises a first p-channel metal-oxide-semiconductor (PMOS) input transistor and a first n-channel metal-oxide-semiconductor (NMOS) input transistor forming two complementary input transistors at the first input node and each configured to receive the first input signal at a gate, and wherein the input comprises a second PMOS input transistor and a second NMOS input transistor forming two complementary input transistors at the second input node and each configured to receive the second input signal at a gate, wherein a drain of the first PMOS input transistor and a drain of the first NMOS input transistor are connected to each other to form an inverter defining a first output node therebetween and wherein a drain of the second PMOS input transistor and a drain of the second NMOS input transistor are connected to each other to form an inverter defining a second output node therebetween;
• providing a first bias current to the first PMOS input transistor and the second PMOS input transistor by at least one PMOS bias transistor, wherein a source of each of the first and the second PMOS input transistor is connected to a drain of the at least one PMOS bias transistor for receiving the bias current, and
• providing a second bias current to the first NMOS input transistor and the second NMOS input transistor by at least one NMOS bias transistor, wherein a source of each of the first and the second NMOS input transistor is connected to a drain of the at least one NMOS bias transistor for receiving a bias current;
• and
• providing control signals to a first and second transistor switch, wherein the first transistor switch is connected between the first or the second output node and a gate of the at least PMOS bias transistor, and wherein the second transistor switch is connected between the first or the second output node and a gate of the at least one NMOS bias transistor, wherein the control signals provided to the first and the second transistor switches control the self-biased amplifier circuit to assume an active mode or a standby mode.