Direct digital synthesizer circuit, measurement system, and method of operating a direct digital synthesizer circuit

Abstract

A DDS circuit includes a phase accumulator circuit. The phase accumulator circuit includes a clock input being configured to receive a clock signal. The phase accumulator circuit includes a frequency tuning register configured to receive a frequency tuning word (FTW), and a phase shift register configured to receive a phase shift word (PSW). The phase accumulator circuit also includes a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator circuit further includes a feedback path configured to feed back the phase signal to the phase increment sub-circuit. The phase accumulator circuit further includes a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word.

Dependencies are inferred from the claim text.