# US 2024/0206191 A1 · Ferroelectric memory device and method for forming the same

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- Number: US 2024/0206191 A1
- Document ID: US20240206191A1
- Status: Published application
- Kind: A1
- Application number: 18/595,939
- Filed: 2024-03-05
- Published: 2024-06-20
- Earliest claimed: 2021-09-08
- Assignees: Wuxi Smart Memories Technologies Co., Ltd.
- Applicants: Wuxi Smart Memories Technologies Co., Ltd.
- Inventors: Meilan Guo; Yushi Hu; Zhenyu Lu; Jianhua Sun
- Web page: https://patentgrep.com/patent/US20240206191A1

## CPC

- H10B 53/30: characterised by the memory core region
- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10B 53/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device includes a plurality of memory cells and a periphery circuit. Each memory cell includes at least one first transistor, at least one first interconnection layer formed over the first transistor and in electrical contact with the at least one transistor, and at least one capacitor electrically coupled to the at least one first transistor through the at least one first interconnection layer. A routing structure disposed over the plurality of memory cells and the periphery circuit to electrically connect the plurality of memory cells and the periphery circuit. A second interconnection layer is disposed over the routing structure. The at least one capacitor is disposed between the routing structure and a topmost conductive layer of the at least one first interconnection layer. The second interconnection layer includes no more than one conductive layer.

## Claims

### Claim 1

A memory device, comprising:
a plurality of memory cells, each memory cell comprising:
at least one first transistor;
at least one first interconnection layer formed over the at least one first transistor and in electrical contact with the at least one first transistor; and
at least one capacitor electrically coupled to the at least one first transistor through the at least one first interconnection layer, comprising:
a first electrode;
a second electrode surrounding at least a first portion of the first electrode, the second electrode electrically contacting the at least one first interconnection layer; and
a ferroelectric layer disposed between the first electrode and the second electrode;
a periphery circuit configured to control operations of the plurality of memory cells;
a routing structure disposed over the plurality of memory cells and the periphery circuit to electrically connect the plurality of memory cells and the periphery circuit; and
a second interconnection layer disposed over the routing structure,
wherein the at least one capacitor is disposed between the routing structure and a topmost conductive layer of the at least one first interconnection layer; and
wherein the second interconnection layer comprises no more than one conductive layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the routing structure comprises a first routing layer in direct contact with the first electrode.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the routing structure comprises a first routing layer in contact with the first electrode through a first via structure.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the ferroelectric layer comprises HfOx, ZrOx, or a combination of HfOx and ZrOx.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the periphery circuit further comprises:
at least one second transistor; and
a plurality of third interconnection layers electrically coupled to the at least one second transistor,
wherein the plurality of third interconnection layers are in contact with the routing structure through at least one second via structure.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the routing structure further comprises a second routing layer coplanar to the first routing layer in contact with the plurality of second interconnection layers through the at least one second via structure.

### Claim 7

A memory device, comprising:
a plurality of memory cells, each memory cell comprising:
at least one first transistor;
at least one first interconnection layer formed over the at least one first transistor and in electrical contact with the at least one first transistor;
a first conductive layer formed over the at least one first interconnection layer, the first conductive layer electrically coupled to the at least one first transistor through the at least one first interconnection layer; and
at least one capacitor formed on the first conductive layer, comprising:
a first electrode;
a second electrode surrounding at least a first portion of the first electrode, the second electrode electrically contacting the first conductive layer; and
a ferroelectric layer disposed between the first electrode and the second electrode; and
a periphery circuit configured to control operations of the plurality of memory cells,
wherein the first electrode of the plurality of memory cells functions as a routing structure between the plurality of memory cells.

### Claim 8 (depends on 7)

The memory device of claim 7, further comprising:
a barrier layer disposed between the first conductive layer and the second electrode.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the barrier layer comprises tantalum or tantalum nitride.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein a width of the barrier layer is equal to or larger than a width of the second electrode.

### Claim 11 (depends on 7)

The memory device of claim 7, wherein the first electrode of one memory cell is in electric contact with the first electrode of another memory cell.

### Claim 12 (depends on 7)

The memory device of claim 7, wherein the periphery circuit further comprises:
at least one second transistor; and
a plurality of second interconnection layers electrically coupled to the at least one second transistor,
wherein the plurality of second interconnection layers are in contact with the routing structure through at least one via structure.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein a first height of the at least one capacitor is equal to or less than a second height of the at least one via structure.

### Claim 14

A method for forming a ferroelectric memory, comprising:
forming a semiconductor structure over a substrate, the semiconductor structure comprising a cell region and a periphery region;
forming a first interconnection structure over the cell region of the semiconductor structure and a second interconnection structure over the periphery region of the semiconductor structure;
forming a dielectric layer over the first interconnection structure and the second interconnection structure;
forming a capacitor in the dielectric layer above the first interconnection structure and a via structure in the dielectric layer above the second interconnection structure; and
forming a routing structure over the capacitor and the via structure.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the capacitor in the dielectric layer above the first interconnection structure and the via structure in the dielectric layer above the second interconnection structure, further comprises:
forming a first opening in the dielectric layer above the first interconnection structure;
forming the capacitor in the first opening, the ferroelectric memory comprising a first electrode, a second electrode surrounding at least a first portion of the first electrode, and a ferroelectric layer disposed between the first electrode and the second electrode;
forming a second opening in the dielectric layer above the second interconnection structure; and
forming the via structure in the second opening.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a linear layer over the capacitor and the via structure.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the routing structure over the capacitor and the via structure, further comprises:
forming a first routing layer in contact with the via structure; and
utilizing a portion of the first electrode as a second routing layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the routing structure over the capacitor and the via structure, further comprises:
forming a first routing layer in contact with the via structure; and
forming a second routing layer in direct contact with the first electrode.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
forming a barrier layer between the first interconnection structure and the capacitor.

### Claim 20 (depends on 19)

The method of claim 19, wherein the barrier layer comprises tantalum or tantalum nitride.