# US 2024/0206166 A1 · Three-dimensional memory device and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0206166 A1 - Document ID: US20240206166A1 - Status: Published application - Kind: A1 - Application number: 18/132,440 - Filed: 2023-04-10 - Published: 2024-06-20 - Earliest claimed: 2022-12-14 - Assignees: Fujian Jinhua Integrated Circuit Co., Ltd. - Applicants: Fujian Jinhua Integrated Circuit Co., Ltd. - Inventors: Shiwei He; Canfa Dai; Detianyu Diao; Guoguo Kong; Hsien-Shih Chu; Yongjian Yu - Web page: https://patentgrep.com/patent/US20240206166A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A three-dimensional memory device includes a substrate and a stack structure including alternating conductive layers and dielectric layers disposed on the substrate, and a memory string structure extending vertically through the stack structure. The memory string structure includes a conductive pillar and a storage layer disposed between the conductive pillar and the stack structure and surrounding the conductive pillar. The storage layer includes a plurality of first protruding portions at interfaces between the conductive layers and the dielectric layers. ## Claims ### Claim 1 A three-dimensional memory device, comprising: a substrate; a stack structure disposed on the substrate and comprising a plurality of alternating conductive layers and dielectric layers; and a memory string structure extending vertically through the stack structure, and comprising: a conductive pillar; and a storage layer disposed between the conductive pillar and the stack structure and surrounding the conductive pillar, wherein the storage layer comprises a plurality of first protruding portions filling first recesses respectively at interfaces between the conductive layers and the dielectric layers. ### Claim 2 (depends on 1) The three-dimensional memory device according to claim 1, wherein the stack structure further comprises a plurality of interfacial layers between bottom surfaces of the conductive layers and the dielectric layers. ### Claim 3 (depends on 2) The three-dimensional memory device according to claim 2, wherein the storage layer further comprises a plurality of second protruding portions filled in second recesses between the interfacial layers, the conductive layers and the dielectric layers, wherein a depth of the second recesses is larger than a depth of the first recesses. ### Claim 4 (depends on 2) The three-dimensional memory device according to claim 2, wherein the conductive layers and the conductive pillar comprise tungsten, the interfacial layers comprise tungsten silicide, and the dielectric layers comprise silicon oxide. ### Claim 5 (depends on 1) The three-dimensional memory device according to claim 1, further comprising: a contact pad disposed in the substrate; and a pad layer disposed between the stack structure and the substrate, wherein the memory string structure extends through the pad layer to directly contact the contact pad. ### Claim 6 (depends on 5) The three-dimensional memory device according to claim 5, wherein the pad layer comprises a metal oxide layer. ### Claim 7 (depends on 1) The three-dimensional memory device according to claim 1, wherein the storage layer comprises a high-k dielectric material. ### Claim 8 (depends on 1) The three-dimensional memory device according to claim 1, wherein corners of the conductive layers that are in direct contact with the first protruding portions have rounded profiles. ### Claim 9 (depends on 1) The three-dimensional memory device according to claim 1, wherein the memory string structure comprises a top portion near a top surface of the stack structure and a bottom portion near a bottom surface of the stack structure that is close to the substrate, and a width of the top portion is larger than a width of the bottom portion. ### Claim 10 (depends on 1) The three-dimensional memory device according to claim 1, wherein a thickness of an upper one of adjacent two of the conductive layers is larger than a thickness of a lower one of the adjacent two of the conductive layers. ### Claim 11 A method for forming a three-dimensional memory device, comprising: providing a substrate; forming a stack structure comprising a plurality of alternating conductive layers and dielectric layers on the substrate; performing an etching process to form a through-hole extending vertically through the stack structure, wherein a sidewall of the through-hole has a plurality of first recesses respectively at interfaces between the conductive layers and the dielectric layers; and forming a memory string structure in the through-hole, wherein the memory string structure comprises a storage layer covering along the sidewall of the through-hole and filling the first recesses and a conductive pillar on the storage layer and filling the through-hole. ### Claim 12 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, wherein the stack structure further comprises a plurality of interfacial layers between bottom surfaces of the conductive layers and the dielectric layers respectively. ### Claim 13 (depends on 12) The method for forming a three-dimensional memory device according to claim 12, further comprising forming a plurality of second recesses on sidewall of the through-hole during the etching process, wherein the second recesses are between the interfacial layers, the conductive layers and the dielectric layers, a depth of the second recesses is larger than a depth of the first recesses. ### Claim 14 (depends on 12) The method for forming a three-dimensional memory device according to claim 12, wherein the conductive layers and the conductive pillar comprise tungsten, the interfacial layers comprise tungsten silicide, and the dielectric layers comprise silicon oxide. ### Claim 15 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, further comprising: forming a contact pad in the substrate; and forming a pad layer on the substrate and covering the contact pad, wherein the through-hole extends through the pad layer, and the memory string structure directly contacts the contact pad. ### Claim 16 (depends on 15) The method for forming a three-dimensional memory device according to claim 15, wherein the pad layer comprises a metal oxide layer. ### Claim 17 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, wherein the storage layer comprises a high-k dielectric material. ### Claim 18 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, wherein corners of the conductive layers exposed from the first recesses have rounded profiles. ### Claim 19 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, wherein the through-hole comprises a top portion near a top surface of the stack structure and a bottom portion near a bottom surface of the stack structure that is close to the substrate, and a width of the top portion is larger than a width of the bottom portion. ### Claim 20 (depends on 11) The method for forming a three-dimensional memory device according to claim 11, wherein a thickness of an upper one of adjacent two of the conductive layers is larger than a thickness of a lower one of the adjacent two of the conductive layers.