US 2024/0205309 A1 · METHOD AND ARCHITECTURE FOR SCALABLE OPEN RADIO ACCESS NETWORK (O-RAN) FRONTHAUL TRAFFIC PROCESSING

Abstract

System and method embodiments are disclosed for scalable open radio access network (O-RAN) fronthaul traffic processing for distributed unit and radio unit. The system may be placed in an O-DU or an O-RU as a scalable O-RAN fronthaul traffic processing unit. O-RAN fronthaul traffic processing may be implemented in unified architecture with hardware-software (HW-SW) interaction in the form of Rx/Tx input descriptors and Rx/Tx output status descriptors. In the transmit direction, fronthaul packets are created with eCPRI header from a symbol memory where RB allocations are stored. In the receive path, from an ingress queues of Ethernet, resource block allocations are created and stored in the symbol memory. The discloses HW-SW interaction mechanism may be agnostic to cores of different architectures, support both RU and DU modes, and provides multiple transport encapsulation formats with scalability to meet various fronthaul traffic processing requirements.

Claims20

Dependent claims

A method for open radio access network (O-RAN) fronthaul traffic processing comprising:

writing one or more transmitting (Tx) input descriptors into a Tx input descriptor buffer, each Tx input descriptor having one or more fields;
fetching, by a Tx input descriptor buffer reader, one or more Tx input descriptors from the Tx input descriptor buffer;
implementing, using one or more acceleration components, Tx flow processing based on at least the fetched one or more Tx input descriptors;
queueing, by a Tx packet writer, processed Tx flow data into a Tx packet memory;
and
pushing the processed Tx flow data queued in the Tx packet memory to one or more egress queues for transmitting through one or more Ethernet lanes.

3 more elements

A system for open radio access network (O-RAN) fronthaul traffic processing comprising:

an Ethernet interface to transmit or receive Ethernet frames, the Ethernet interface comprises a transmitting (Tx) packet memory, a receiving (Rx) packet memory, a Tx Ethernet direct memory access (DMA) descriptor buffer, and an Rx Ethernet DMA descriptor buffer;
a symbol memory storing resource block (RB) allocations;
and
one or more acceleration components implementing Tx flow processing, Rx flow processing, or a combination of both Tx and Rx flow processing, with hardware-software (HW-SW) interaction in the form of input descriptors and output status descriptors, the one or more acceleration components comprise:
a Tx input descriptor buffer reader that fetches, from a Tx input descriptor buffer, one or more Tx input descriptors for Tx flow processing based on at least the fetched one or more Tx input descriptors;
and
a Tx output status writer that writes a Tx output status regarding the Tx flow processing into a Tx output status buffer;
a Rx input descriptor buffer reader that fetches, from a Rx input descriptor buffer, one or more Rx input descriptors for Rx flow processing based on at least the fetched one or more Rx input descriptors;
and
a Rx output status writer that writes a Rx output status regarding the Rx flow processing into a Tx output status buffer.

7 more elements

Dependencies are inferred from the claim text.

Method and architecture for scalable open radio access network (o-ran) fronthaul traffic processing

Life of this patent

Method and architecture for scalable open radio access network (o-ran) fronthaul traffic processing

Life of this patent

Abstract

Claims20