# US 2024/0205167 A1 · System-in-package network processors

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- Number: US 2024/0205167 A1
- Document ID: US20240205167A1
- Status: Published application
- Kind: A1
- Application number: 18/587,744
- Filed: 2024-02-26
- Published: 2024-06-20
- Earliest claimed: 2019-03-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kevin Clark; Scott J. Weber; Ravi Prakash Gutala; Aravind Raghavendra Dasu
- Web page: https://patentgrep.com/patent/US20240205167A1

## CPC

- H04L 49/109: Integrated on microchip, e.g. switch-on-chip
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- H03K 19/17758: for speeding up configuration or reconfiguration
- H03K 19/1776: for memories
- H04L 49/15: Interconnection of switching modules
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

## Claims

### Claim 1

An integrated circuit device comprising:
a base die that comprises memory; and
an application-specific integrated circuit die coupled to the base die via an interface, wherein the application-specific integrated circuit die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the application-specific integrated circuit die with a region of the application-specific integrated circuit die being vertically aligned with a corresponding region-aligned memory of the memory of the base die that is allocated to the region, wherein the application-specific integrated circuit die is to implement a processing function that uses the region-aligned memory.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the processing function employs a data structure for performance of the processing function or a data packet to be processed by the processing function, or both, and wherein the base die stores the data structure, the data packet, or both.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein the interface comprises a high-density interconnect, a 3D interconnect, or a microbump interconnect.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the application-specific integrated circuit die is to implement a processor.

### Claim 5 (depends on 4)

The integrated circuit device of claim 4, wherein the processor is implemented in the region of the application-specific integrated circuit die and accesses a data structure or data packet stored in a first region-aligned memory circuitry associated with the region.

### Claim 6 (depends on 4)

The integrated circuit device of claim 4, wherein the processor is implemented in the region of the application-specific integrated circuit, a data structure is stored in a second region-aligned memory, and the processor accesses the data structure using a network-on-chip (NOC) of the base die.

### Claim 7 (depends on 1)

The integrated circuit device of claim 1, wherein the application-specific integrated circuit die is to implement a network processor.

### Claim 8 (depends on 7)

The integrated circuit device of claim 7, wherein the application-specific integrated circuit die is configured to implement a programmable logic in the application-specific integrated circuit die.

### Claim 9 (depends on 7)

The integrated circuit device of claim 7, wherein the network processor is to implement a quality of service (QOS) functionality, a packet filtering functionality, a packet routing, an encryption functionality, a decryption functionality, an error checking functionality, a direct memory access management functionality, or a look-up table functionality, or a combination thereof.

### Claim 10

A system comprising:
a memory; and
a processing device comprising:
a base die that comprises on-package memory comprising a plurality of regions; and
a processor die having a plurality of regions, wherein the processor die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the processor die with the plurality of regions of the base die vertically aligned to corresponding regions of the plurality of regions of the processor die, and the processing device is operable to execute processes using data from the base die.

### Claim 11 (depends on 10)

The system of claim 10, wherein the processor die comprises an application-specific integrated circuit (ASIC) or a general-purpose processor, or any combination thereof.

### Claim 12 (depends on 10)

The system of claim 10, wherein the processing device is configured to:
implement a first function configured to exchange data with the on-package memory in the base die using a high-speed interface between the processor die and the base die; and
utilize buffer manager circuitry configured to exchange data with the memory.

### Claim 13 (depends on 12)

The system of claim 12, wherein the first function comprises processing header data, and wherein the buffer manager circuitry processes payload data and stores a link data structure that associates a header of the header data with a payload of the payload data.

### Claim 14 (depends on 12)

The system of claim 12, wherein the buffer manager circuitry exchanges payloads with the memory or references to payloads with the memory.

### Claim 15 (depends on 12)

The system of claim 12, wherein the processor die is programmable to swap the first function for a second function in the processor die.

### Claim 16 (depends on 10)

The system of claim 10, wherein the processing device comprises a data bridge that receives data in a first protocol and transmits data in a second protocol different from the first protocol.

### Claim 17 (depends on 10)

The system of claim 10, comprising an interface that comprises a high-density interconnect, a 3D interconnect, or a microbump interconnect between the base die and the processor die.

### Claim 18

A system comprising:
a memory die that comprises on-package memory comprising a plurality of regions; and
a network processor die to implement a network processor and having a plurality of regions, wherein the processor die and the memory die are vertically aligned so the memory die is vertically below at least a portion of a surface area of the processor die with the plurality of regions of the memory die vertically aligned to corresponding regions of the plurality of regions of the network processor die, and the network processor is operable to execute processes using data from the memory die.

### Claim 19 (depends on 18)

The system of claim 18, wherein the network processor is to:
implement a first virtual network function (VNF) profile that comprises a first processing function;
switch from the first processing function to a second processing function; and
implement a second VNF profile that comprises the second processing function.

### Claim 20 (depends on 19)

The system of claim 19, wherein the first processing function and the second processing function each comprise at least one of a quality of service (QOS) functionality, a packet filtering functionality, a packet routing, an encryption functionality, a decryption functionality, an error checking functionality, a direct memory access management functionality, or a look-up table functionality, or a combination thereof, and the first processing function and the second processing functions are different.