# US 2024/0204064 A1 · Dielectric barrier for backside interconnect separation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2024/0204064 A1 - Document ID: US20240204064A1 - Status: Published application - Kind: A1 - Application number: 18/084,844 - Filed: 2022-12-20 - Published: 2024-06-20 - Earliest claimed: 2022-12-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Guillaume Bouche; Bilal Chehab; Lars Liebmann; Quan Shi - Web page: https://patentgrep.com/patent/US20240204064A1 ## CPC - H10D 30/6729: {characterised by the electrodes} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/01: Manufacture or treatment - H10D 84/0167: {Manufacturing their channels} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 84/852: {comprising forksheet IGFETs} - H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques are provided herein to form semiconductor devices having a dielectric wall or spine between two devices that extends between source or drain regions of the two devices and separates backside contacts to the source or drain regions. A first semiconductor device includes a first semiconductor region extending from a first source or drain region and a second adjacent semiconductor device includes a second semiconductor region extending from a second source or drain region adjacent to the first source or drain region. A dielectric wall extends between the first source or drain region and the second source or drain region. A first backside contact touches the underside of the first source or drain region and a second backside contact touches the underside of the second source or drain region. The dielectric wall further extends down between the first conductive contact and the second conductive contact. ## Claims ### Claim 1 An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region, the second source or drain region being adjacent to the first source or drain region along the second direction; a first conductive contact on an underside of the first source or drain region and a second conductive contact on an underside of the second source or drain region; and a dielectric wall extending in the first direction between and contacting both the first semiconductor region and the second semiconductor region, and extending between both the first source or drain region and the second source or drain region, wherein the dielectric wall further extends in a third direction along at least an entire thickness of the first conductive contact and the second conductive contact. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the dielectric wall directly contacts a sidewall of the first conductive contact and a sidewall of the second conductive contact. ### Claim 3 (depends on 1) The integrated circuit of claim 1, further comprising a first conductive layer on the first conductive contact and a second conductive layer on the second conductive contact, wherein the dielectric wall extends in the third direction between the first conductive layer and the second conductive layer. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising a first dielectric fill on a topside of the first source or drain region and a second dielectric fill on a topside of the second source or drain region, wherein the dielectric wall extends in the third direction between the first dielectric fill and the second dielectric fill. ### Claim 5 (depends on 1) The integrated circuit of claim 1, further comprising a dielectric layer adjacent to the first conductive contact and the second conductive contact. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the dielectric wall has a width in the second direction between about 5 nm and about 30 nm. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the second direction is substantially perpendicular to the first direction and wherein the third direction is substantially perpendicular to both the first and second directions. ### Claim 8 (depends on 1) A printed circuit board comprising the integrated circuit of claim 1. ### Claim 9 An electronic device, comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a first semiconductor device having a first semiconductor region extending in a first direction between a first source or drain region and a second source or drain region, and a first gate structure extending in a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending in the first direction between a third source or drain region and a fourth source or drain region, and a second gate structure extending in the second direction over the second semiconductor region; a first conductive contact on an underside of the first source or drain region and a second conductive contact on an underside of the third source or drain region; and a dielectric wall extending in the first direction between and contacting both the first semiconductor region and the second semiconductor region, extending in the first direction between the first source or drain region and the third source or drain region, and extending in the first direction between the second source or drain region and the fourth source or drain region, wherein the dielectric wall further extends in a third direction along at least an entire thickness of the first conductive contact and the second conductive contact. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the dielectric wall directly separates the first conductive contact from the second conductive contact. ### Claim 11 (depends on 9) The electronic device of claim 9, further comprising a first conductive layer on the first conductive contact and a second conductive layer on the second conductive contact, wherein the dielectric wall extends in the third direction directly between the first conductive layer and the second conductive layer. ### Claim 12 (depends on 9) The electronic device of claim 9, further comprising a first dielectric fill on a topside of the first source or drain region and a second dielectric fill on a topside of the third source or drain region, wherein the dielectric wall extends in the third direction directly between the first dielectric fill and the second dielectric fill. ### Claim 13 (depends on 9) The electronic device of claim 9, wherein the first semiconductor region comprises a plurality of first semiconductor nanosheets and the second semiconductor region comprises a plurality of second semiconductor nanosheets. ### Claim 14 (depends on 9) The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board. ### Claim 15 An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor region, the second source or drain region being adjacent to the first source or drain region along the second direction; a dielectric layer beneath the first source or drain region and the second source or drain region; a first conductive contact extending through an entire thickness of the dielectric layer and contacting an underside of the first source or drain region, and a second conductive contact extending through the entire thickness of the dielectric layer and contacting an underside of the second source or drain region; and a dielectric wall extending in the first direction between the first source or drain region and the second source or drain region, wherein the dielectric wall further extends in a third direction between the first conductive contact and the second conductive contact. ### Claim 16 (depends on 15) The integrated circuit of claim 15, further comprising a first conductive layer on the first conductive contact and a second conductive layer on the second conductive contact, wherein the dielectric wall extends in the third direction directly between the first conductive layer and the second conductive layer. ### Claim 17 (depends on 15) The integrated circuit of claim 15, further comprising a first dielectric fill on a topside of the first source or drain region and a second dielectric fill on a topside of the second source or drain region, wherein the dielectric wall extends in the third direction directly between the first dielectric fill and the second dielectric fill. ### Claim 18 (depends on 15) The integrated circuit of claim 15, wherein the dielectric wall has a width in the second direction between about 5 nm and about 30 nm. ### Claim 19 (depends on 15) The integrated circuit of claim 15, wherein the second direction is substantially perpendicular to the first direction and wherein the third direction is substantially perpendicular to both the first and second directions. ### Claim 20 (depends on 15) A printed circuit board comprising the integrated circuit of claim 15.